IEC 61131-3 — logic the commissioning engineer can read
The international standard for controller programming languages. A program in it is clear to any control systems engineer who knows the standard.
Controller programming languages
IEC 61131-3 is the third part of the standard on programmable controllers. It defines the languages logic is written in and the structure of a program: what program units exist, data types, how blocks are called.
For the customer this means one thing: a program written by the standard can be read and edited by an engineer familiar with any environment that supports the standard. The logic is not locked in one supplier’s language.
In SyncTwin the standard is the only language of unit logic: the former own unit language has been retired, production programs moved to ST and SFC. A unit does not execute G-code — it calls a cutting program with a block.
- SFC — sequenceSteps, transitions on conditions, actions in steps: the unit cycle reads like a diagram.
- ST — structured textCalculations and conditions — as text similar to familiar languages.
- Function blocksReusable blocks with inputs and outputs; PLCopen adds axis motion blocks.
- Program exchangePLCopen XML is the format for moving programs between environments.
Languages and program units
| Element of the standard | What it is | With us |
|---|---|---|
| SFC | Sequential function chart: steps, transitions, actions | works — unit logic and cell procedure, player in the lab |
| ST | Structured text | works — unit logic, transition conditions |
| LD, FBD | Ladder and function block diagrams | Programs are brought in ST or SFC |
| Program | The top unit executed by a controller task | Unit program; language is its property |
| Function block | A unit with memory, inputs and outputs | PLCopen motion blocks, motion techniques |
| Variables with a range | Program input variables | Unit knobs: range and units, values stored with the unit |
The text is checked by the compiler in full against the standard, then the binding to the unit. Errors are shown as is, with their place in the text.
One language for unit and cell logic
- Unit logic — SFC or STThe cell procedure is also SFC: a cell step is a unit, a phase command and a completion condition.
- Motion — PLCopen blocksAxis move, reset, error reading — with standard blocks.
- Compiler checkingThe text is checked in full against the standard; an error comes with its place in the text.
- Import.st and PLCopen XML files; with several programs in a file — choosing the right one.
- Runs on the test benchUnit programs run on the test bench as IEC 61131-3 programs.
Logic in SFC, motion in a block
Timers, waits, signal conditions, interlocks, counters and PackML states live in SFC. Motion lives in a function block: the program says “transfer” and the block calculates the path.
| PLCopen block | What it does |
|---|---|
| MC_Power | Axis enable; ANDed with unit power; off — the axis is disabled |
| MC_MoveAbsolute and others | Axis motion; the block has Active, acceleration and deceleration |
| MC_Reset | Axis fault reset |
| MC_ReadAxisError | Reading the axis error |
| MC_SetPosition | Coordinate shift without motion |
A verb is a block too
Transfer, flip and placement are available to the unit program as function blocks. A machine’s cutting program is called with a start block.
An interface like PLCopen
The platform’s goal is every motion verb with an “Execute → Busy → Done or Error” interface, inputs being the verb parameters.
The program does not know the executor
The block name is one; which equipment executes it is decided at start. No match — a refusal with the reason.
How the standard looks in a unit program
| SFC step | Action | Transition |
|---|---|---|
| home | Both positioner axes to 0° — MC_MoveAbsolute on each | Both blocks Done |
| tilt | Table tilt to 45° | Done |
| turn | Faceplate rotation by 360° | Done |
| tilt back | Both axes to 0° simultaneously | Both blocks Done |
| pause | Timer delay | Timer → “home” |
The final SFC step is the unit’s PackML Complete state. Example walkthrough and fault thresholds — “PLC programs”.
Four stages before the axis moves
- CompilerThe full text against the standard, then the binding to the unit: axes, roles, I/O names.
- LabInput table %IX and output table %QX, input forcing, SFC player, PackML state.
- Virtual axesSteps, timing and transitions — on the test bench, drives stand still.
- DrivesFollowing error and load — only on a real axis.
Forcing is a debugging tool following the rules of controller programming environments: it is cleared on emergency stop and never goes into production.
Questions about the language
Can we bring a ready program from our environment?
Yes, as ST text or a PLCopen XML file. If the file has several program units, the platform asks which one to take; the compiler shows what did not pass, with its place in the text.
Will our commissioning engineer be able to edit the program without you?
The program is written in the language of the standard; SFC steps and transitions read like a diagram. What is handed over to your team is fixed in the implementation specification.
Where can I see what the program is doing now?
The SFC player in the lab highlights the step, the “Unit” panel shows inputs, outputs and PackML state, the run log shows how a start ended.
What about ladder diagrams?
Unit logic is written in SFC or ST. Your program in another language of the standard is moved into them within the implementation.
Where are speeds and delays stored?
In the unit knobs — input variables with a range and units. The “Visual” view shows them for any language; values are stored with the unit, not in the text.
What works and what is in preparation
- RunsST and SFC, import of .st and PLCopen XML, compiler, lab, execution on the test bench on virtual axes and on drives.
- In preparationA transfer block with points as a table, an output confirmation watchdog.
- Canon and goalAll motion verbs as function blocks with a PLCopen interface.
Discuss an implementation
Send a unit program in ST or PLCopen XML — we will check it with the compiler and in the lab and propose an R&D stage.
Request accessDiscuss an implementation
Describe the unit or line — we will tell you what we will verify and in what time. Target indicators are fixed in the implementation specification.
Request access